1. Technical Field
The present disclosure relates to a method of fabricating a vertical MOS transistor, and a transistor fabricated thereby. The disclosure also relates to a memory cell comprising such a transistor.
2. Description of the Related Art
Integrated circuits have traditionally been fabricated with planar transistors. However, vertical transistors are becoming more common, as they allow smaller transistor sizes and can more easily be stacked, for example for stacked memory cell applications.
FIGS. 1A and 1B are cross-sectional views showing conventional steps of fabrication of a vertical transistor. FIG. 1A shows a step S1, wherein a semiconductor substrate 1 comprising a doped region 2 serves as a base for a vertical transistor structure. Dielectric layers 3 (3-1, 3-2, 3-3) are deposited on the top surface of the substrate, and a conductive layer 4 comprising outer lateral edges 4′ is formed in the dielectric layer 3-2. A hole 5 is then etched through the dielectric layers 3 and the conductive layer 4, exposing an inner lateral edge 4″ of the conductive layer and a portion 1′ of the top surface of the substrate.
FIG. 1B shows a step S2, wherein a thermal oxidation is performed. A gate oxide 6 forms on the inner lateral edge 4″ of the conductive layer and a bottom oxide 7 also forms on the portion 1′ of the top surface of the substrate. A semiconductor material may then be deposited in the hole 5, forming a vertical MOS (“metal-oxide-semiconductor”) transistor.
Nevertheless, unless removed beforehand, the bottom oxide 7 prevents electrical contact between the semiconductor material in the hole and the doped region 2. Therefore, the bottom oxide 7 may be etched, such as by means of a reactive ion etch process, but the gate oxide 6 may be damaged in the etching process. An alternative is to form a cavity below the transistor structure, filled with a “sacrificial material”, such as nitride, that does not oxidize and may then be removed by means of a wet etch process. The cavity can then be re-filled with a semiconductor material. Nevertheless, the chemical used for etching may contaminate the surfaces of the transistor, and the small diameter and total depth of the hole 5 limit the access to the cavity for etching and refilling.
It may therefore be beneficial to provide an alternative method of fabricating a vertical transistor.